1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate in a semiconductor device, which can improve the characteristics of the device.
2. Description of the Prior Art
Currently, as the size of a semiconductor device becomes smaller, it is more and more difficult to secure the capacity of a capacitor. Also, as the magnitude of electric field in the junction regions of a transistor becomes larger, it is more and more difficult to secure the refresh characteristics of a cell area. For this reason, a method is used which makes the effective channel length of a transistor by the use of a three-dimensional cell other than a planar cell.
Particularly, a structure was recently proposed in which the capacitor contact region of a substrate is placed lower than the bit-line contact region by forming the gate after recessing a portion of the edge region of the active region of the substrate, and thus, the effective channel length required for the operation of the gate is increased. This structure shows an increase in the threshold voltage by an increase in channel length, thus an improvement in the refresh characteristics.
FIGS. 1A to 1E are cross-sectional views for explaining a method for forming a gate in a semiconductor device according to the prior art.
As shown in FIG. 1A, the silicon substrate 10 having active and field regions is provided, and then, the isolation film 11 is formed on the field region of the substrate 10. Next, on the silicon substrate 10 including the isolation film 11, the first photoresist pattern 12 exposing the edge portion of the active region is formed.
As shown in FIG. 1B, the silicon substrate 10 is then etched using the first photoresist pattern 12 as an etch barrier so as to form the trench 13. Following this, the first photoresist pattern 12 is removed.
As shown in FIG. 1C, the gate oxide film 14, the silicon film 15, the tungsten silicide film 16 and the hard mask film 17 are sequentially formed on the resulting structure. At this time, the thickness of a portion on the trench 13, i.e., the thickness of a portion of the silicon film 15 formed on the etched portion of the substrate 10, is larger than the thickness of a portion of the silicon film 15 formed on the unetched portion of the substrate 10. Then, the second photoresist pattern 18 defining a gate formation region is formed on the hard mask film.
As shown in FIG. 1D, the hard mask film 17, the tungsten silicide film 16, the silicon film 15 and the gate oxide film 14 are selectively etched using the second photoresist pattern 18 as an etch barrier so as to form the gate 19 covering the corner portion of the trench 13. Then, the second photoresist pattern 18 is removed. In FIG. 1D, reference numerals 14a, 15a, 16a and 17a designate the gate oxide film remaining after the etching, the silicon film remaining after the etching, the tungsten silicide film remaining after the etching, and the hard mask film remaining after the etching, respectively.
Thereafter, in order to recover from damage caused by the etching step for forming the gate 19, the silicon substrate 10 including the gate 19 is subjected to the thermal oxidation process 20.
As shown in FIG. 1E, an insulating film (not shown) for forming gate spacers is then formed on the resulting structure by a thermal process. Next, the gate spacer-forming insulating film is etched to form the gate spacers 21 on both sidewalls of the gate 19.
FIG. 2 is a cross-sectional view showing problems occurring in the prior art.
In the method for forming the gate in the semiconductor device according to the prior art, however, the volume of the silicon film 15a and the tungsten silicide film 16a shrinks in the thermal oxidation process 20 and the thermal process for forming the spacers 21. Also, since the thickness of a portion of the silicon film 15a and the tungsten silicide film 16a placed on the trench is greater than the thickness of a portion of the silicon film 15a and the tungsten silicide film 16a placed on the unetched portion of the substrate, the volume of a portion of the silicon film 15a and the tungsten silicide film 16a placed on the trench 13 relatively greatly shrinks. Thus, as shown in FIG. 2, the gates 20 lean to the trench 13 (see arrow). Due to the leaning of the gates 20, the interval between the gates 20 becomes narrow, and thus, contact open failure in the formation of a landing plug contact will occur. Also, an interlayer insulating film to be formed subsequently does not completely fill the space between the gates 20, so that a bridge between plugs can occur. As a result, the characteristics of the device will be deteriorated.